1. Field of the Invention
This invention relates generally to computer systems and more specifically to a technique for ensuring undesired command sequences are not inadvertently sent out on a bus due to a slowly ramping or otherwise low logic supply voltage.
2. Description of the Related Art
In a typical processor device, such as a central processor unit (CPU) or graphics processing unit (GPU), different logic portions may be powered from different supply voltages. For example, in a GPU, core processing logic that processes data and generates command signals to external devices (e.g., memory devices) may be powered from a first supply voltage (e.g., VDD), while input output (I/O) logic that drives those command signals onto I/O pads may be powered from a second supply voltage (e.g., VDDP). In an effort to conserve power and increase operating frequency, the supply voltage used to power the core logic may be lower than the supply voltage used to power the I/O logic.
Unfortunately, during power up or power down of the device, the I/O supply voltage may reach its final value while the core supply voltage is still ramping up or is completely off. Under such conditions, control signals supplied by the core logic to be driven onto the I/O pads by the I/O logic, which are driven to core voltage supply levels, may not set to correct levels. Because the I/O supply voltage is ramped up to the final level, incorrect signal levels may be driven onto the I/O pad outputs connected to the bus between GPU and memory devices. In some cases, one or more control signals used to latch commands to a memory device, such as a clock signal (CK), clock enable signal (CKE), or chip select signal (CS), may inadvertently toggle while undetermined values are present on other signal lines whose logic levels define the commands. As a result, certain command or command sequences may be inadvertently sent to the memory devices, which may place them in an inoperable (“locked”) state. In some cases, it may not be possible to recover from this inoperable state without applying a system level reset and/or otherwise applying a correct power sequence.
In some conventional systems, this situation has been addressed by generating an external control signal which is at I/O supply voltage level and is indicative of the core logic supply voltage level. This external control signal may be distributed to all the I/O pad driver circuits internally and used to keep the I/O pads in a high impedance state (tristate) until the final core logic supply voltage level has been reached. This approach is suboptimal because it requires the additional circuitry for generating such a signal and adds complexity as the signal must be distributed across all the pads within the I/O pad routing section (ring) of the GPU die.
Another approach is to utilize external components to ensure a proper power sequence is achieved. For example, circuit components may be arranged to ensure the core logic supply voltage supplied to the device has reached a final level before the I/O logic supply voltage is supplied to the device. However, this approach is also suboptimal as it adds components to the system bill of materials (BOMs) and increases overall cost and complexity.
Accordingly, what is needed is an improved technique to avoid the problems encountered when core logic and I/O logic supply voltages reach final voltage levels at different times.